1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor device and more particularly, to a fabrication method of a semiconductor device equipped with a semiconductor layer with a hemispherical-grained (HSG) configuration, which is preferably applied to fabrication of dynamic random-access memories (DRAMs) necessitating very large capacitance.
2. Description of the Prior Art
In recent years, to raise the integration level of electronic elements in DRAMs, there has been the strong need to increase the capacitance per chip area of memory cell capacitors. To cope with this need, the top or bottom electrode of each memory cell capacitor has been formed to have a solid or three-dimensional shape such as a cylinder.
Moreover, to increase the surface area of the bottom electrode, the use of a silicon (Si) layer with a HSG configuration (i.e., a HSG Si layer) has been studied to increase the surface irregularities of the bottom electrode, thereby roughening positively the surface of the bottom electrode. In this case, however, if the HSG Si layer is depleted during operation of the memory cell capacitor, the electric resistance of the HSG Si layer increases, which means that any satisfactory capacitance increase is unable to be realized. As a result, it has been usual that a suitable impurity or dopant such as phosphorus (P) is introduced into the HSG Si layer by a conventional diffusion or ion-implantation process, thereby lowering the electric resistance of the HSG Si layer.
Japanese Non-Examined Patent Publication No. 9-289292 published in November 1997 discloses fabrication methods of a semiconductor device equipped with a surface-roughened polysilicon layer similar to the HSG Si layer.
One of these prior-art methods thus disclosed is comprised of a first step of forming an interlayer dielectric layer on or over a semiconductor substrate, a second step of forming a contact hole in the interlayer dielectric layer to uncover the underlying substrate, a third step of forming a surface-roughened polysilicon (poly-Si) layer on the interlayer dielectric layer to cover the contact hole, a fourth step of forming a phosphosilicate glass (PSG) layer on the surface-roughened poly-Si layer, a fifth step of diffusing phosphorus (P) atoms contained in the PSG layer into the surface-roughened poly-Si layer as a dopant, and a six step of removing the PSG layer from the surface-roughened poly-Si layer.
In the fifth step, the diffusion of the P atoms into the surface-roughened poly-Si layer is carried out by a heat treatment process at a comparatively high temperature of approximately 800 to 950.degree. C. for approximately 10 to 60 minutes.
Incidentially, to fabricate a DRAM incorporated with logic circuits, heat treatment processes are necessary to be carried out at a temperature as low as possible for a time as short as possible, thereby preventing the logic circuits (especially, transistors provided in the logic circuits) from being thermally damaged.
With the above-described prior-art fabrication method disclosed in Japanese Non-Examined Patent Publication No. 9-289292, however, the fifth step of diffusing the P atoms into the surface-roughened polysilicon layer is carried out at a high temperature of approximately 800.degree. C. to 950.degree. C. for a long time of approximately 10 to 60 minutes. Therefore, this prior-art method is unable to be applied to fabrication of the DRAM incorporated with the logic circuits.
Also, since the fifth step of diffusing the P atoms into the surface-roughened poly-Si layer is carried out at a high temperature of approximately 800.degree. C. to 950.degree. C. in the prior-art method, the Si atoms existing in the surface-roughened poly-Si layer are likely to be consumed during to the progress of the thermal oxidation of the PSG layer through the fifth step, resulting in a problem that the surface roughness of the surface-roughened poly-Si layer is decreased.
As described above, in fabrication of a DRAM incorporated with logic circuits, the protection of the logic circuits and the prevention of the surface-roughness decrease of the surface-roughened poly-Si layer are in a trade-off relationship with the suitable doping or introduction of the dopant into the surface-roughened poly-Si layer.